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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||| 4 channel i2c bus multiplexer with interrupt logic 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 1 pi4 msd5v954 4a features ? 1 - of - 4 bidirectional translating multiplexer ? i2c - bus interface logic; ? operating power supply voltage : 1.65 v to 5.5 v ? allows voltage level translation between 1.2v, 1.8v,2 .5 v, 3.3 v and 5 v buses ? low standby current ? low ron switches ? channel sele ction via i2c bus ? power - up with all multiplexer channels deselected ? capacit ance isolat ion when channel disabled ? no glitch on power - up ? supports hot insertion ? 5 v tolerant inputs ? 0 hz to 400 khz clock frequency ? esd protection exceeds 8 000 v hbm per jesd22 - a114, and 1000 v cdm per jesd22 - c101 ? latch - up testing is done to jedec standard jesd78 which exceeds 100 ma ? packages offered: tssop - 20 l description t he PI4MSD5V9544A is a 1 - of - 4 bidirectional translating multiplex er, controlled via the i2c bus . the scl/s da upstream pair fans out to four scx/sdx downstream pairs, or channels. pin configuration only one scx/sdx channel is selected at a time, determined by the contents of the programmable control register. four interrupt inputs, int0 to int3, one for each of the scx/sdx downstream pairs, are provided. one interrupt output, int, which acts as an and of the four interrupt inputs, is provided. a power - on reset function puts the registers in their default state and initializes the i2 c bus s tate machine with no channels selected. the pass gates of the multiplexer are constructed such that the vcc pin can be used to limit the maximum high voltage which will be passed by the PI4MSD5V9544A . this allows the use of different bus voltages on each scx/sdx pair, so that 1.2v, 1.8 v, 2.5 v or 3.3 v parts can communicate with 5 v parts without any additional protection. external pull - up resistors pull the bus up to the desired voltage level for each channel. a ll i/o pins are 5 v tolerant. pin de scription pin no pin name type description 1 a 0 input address input 0 2 a 1 input address input 1 3 a2 input address input 2 4 i nput active low interrupt input 0 5 sd0 i/o serial data 0 6 sc0 i/o serial clock 0 7 i nput active low interrupt input 1 8 sd1 i/o serial data 1 9 sc1 i/o serial clock 1 10 gnd ground supply ground 11 in put active low interrupt input 2 12 sd2 i/o serial data 2 13 sc2 i/o serial clock 2 14 input active low interrupt input 3 15 sd3 i/o serial data 3 16 sc3 i/ o serial clock 3 17 output active low interrupt output 18 scl i/o serial clock line 19 sda i/o serial data line 20 vcc power power supply tssop 2 0 int0 int 1 int 2 int 3 int
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 2 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic block diagram figure 1: block diagram maximum ratings storage temperature .............. ............... ........... ......... C 5 5c to +1 25 c supply voltage port b ...... ......................................... .. C 0.5v to + 6.0 v supply voltage port a ........ ........................................ C 0.5v to + 6.0 v dc input voltage ......................... ....... ....................... C 0.5v to +6 .0 v control input voltage (en ) ...... ..................... ....... C 0.5v to +6 .0 v t otal power dissipation (1) ............. ...................................... .... 100mw i nput current (en,vcca,vccb,gnd) .............. ..... .............. .... 50ma esd: hbm mode ............. ................................................. ....... 8000v recommended operation conditions symbol parameter min typ max unit v cc v cca positive dc supply voltage 1.65 - 5.5 v v en enable control pin v oltage gnd - 5.5 v v io i/o pin voltage gnd - 5.5 v t /v input transition rise or fall time - - 10 ns/v t a operating temperature range ? 40 - +85 c note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi - tions above those indicated in the operational sec - tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 3 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic dc electrical characteristics unless otherwise specified, - 40ct a 8 5c , 1. 1 v vcc 3.6 v symbol parameter conditions vcc min typ max unit supply vcc s upply voltage 1.65 5.5 v icc supply current operating mode; no load; v i = vcc or gnd ; fscl = 100 khz 3.6v to 5.5v 65 100 ua 2.3v to 3.6v 20 50 ua 1.65v to 2.3v 10 30 ua istb standby current standby mode; vcc = 3.6 v; no load; v i = vcc or gnd; fscl = 0 khz 3.6v to 5.5v 0.3 1 ua 2.3v to 3.6v 0.1 1 ua 1.65v to 2.3v 0.1 1 ua vpor [1] power - on reset voltage no load; v i = vcc or gnd 3.6v to 5.5v 1.3 1.5 v input scl; input/output sda v il low - level input voltage 1.65v to 5 .5v - 0.5 +0.3 v cc v v ih high - level input voltage 1.65v to 2v 0.75 v cc 6 v 2v to 5.5v 0.7 v cc 6 v i ol low - level output current v ol = 0.4 v 1.65v to 5.5v 3 - ma v ol = 0.6 v 1.65v to 5.5v 6 - ma i il low - level input current v i = gnd 1.65v to 5 .5v - 1 +1 ua i ih high - level input current v i = vcc 1.65v to 5.5v - 1 +1 ua ci input capacitance vi = gnd 3.6v to 5.5v - 12 13 pf pass gate ron on - state resistance v o = 0.4 v; i o = 15 ma 4.5 v to 5.5 v 4 9 24 o = 0.4 v; i o = 1 0 ma 2.3v to 2.7v 7 16 55 l leakage current vi = vcc or gnd 1.65v to 5.5v - 1 +1 ua cio input/output capacitance vi = vcc or gnd 1.65v to 5.5v 3 5 pf t o be continued
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 4 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic continued symbol parameter conditions vcc min typ max unit select inputs a0, a1, a2, int0, int1 ,int2,int3 v il low - level input voltage 1.65v to 5.5v - 0.5 +0.3 v cc v v ih high - level input voltage 1.65v to 5.5v 0.7 v cc 6 v i il low - level input current v i = gnd 1.65v to 5.5v - 1 +1 ua ci input capacitance v i = gnd 1.65 v to 5.5v 3 5 pf int output i o l low - level out put current v ol = 0.4 v 1.65v to 5.5v 3 ma i o h high - level out put current 1.65v to 5.5v +10 ua note : vcc must be lowered to 0.2 v for at least 5 u s in order to reset part. ac electrical characteristics tamb = - 40 o c to +85 o c; unless otherwise specified. symbol parameter conditions vcc min typ max unit t pd [1] propagation delay f rom sda to sdx, or scl to scx 1.65v to 5.5v 0.3 ns int [2] t v _int valid time from intn to int signal 1.65v to 5.5v 4 us t d _int delay time from intn to int inactive 1.65v to 5.5v 2 us t rej_l low - level rejection time 1.65v to 5.5v 1 us t rej_ h high - level rejection time 1.65v to 5.5v 0.5 us note [1] pass gate propagation delay is calculated from the 20 typical ron and the 15 pf load capacitance. [2] measurements taken with 1 kpull - up resistor and 50 pf load.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 5 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic i2c interface timing requirements symbol parameter standard mode i 2 c bus fast mode i 2 c bus unit min max min max fscl i2c clock frequenc y 0 100 0 400 khz t low i2c clock high time 4 .7 1.3 s high i2c clock low time 4 0.6 s sp i2c spike time 50 50 ns t su:dat i2c serial - data setup time 250 100 ns t hd :dat i2c serial - data hold time 0 [1] 0 [1] s buf i2c bus free time between stop and start 4.7 1.3 s su:sta i2c start or repeated start condition setup 4.7 0.6 s hd:sta i2c start or repeated start condition hold 4 0.6 s su:sto i2c stop con dition setup 4 0.6 s vd:dat valid - data time (high to low) [3] scl low to sda output low valid 1 1 s [3] scl low to sda output high valid 0.6 0.6 s vd:ack valid - data time of ack condition ack signal from scl low to sda output low 1 1 s notes: [1] a device internally must provide a hold time of at least 300 ns for the sda signal (referred to as the vih min of the scl signal), in order to bridge the undefined reg ion of the falling edge of scl. [ 2 ] data taken using a 1 - k? pullup resistor and 50 - pf load notes figure 2 . definition of timing on the i2c - bus
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 6 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic application figure 3 . typical application vcc vpu1 vpu2 1.8v 1. 5 v - 5.5v 1.2v - 5.5v 2.5v 1.8 v - 5.5v 1.8v - 5.5v 3.3v 2.7v - 5.5v 2.7v - 5.5v 5v 4.5v - 5.5v 4.5v - 5.5v note: if the device generating the interrupt has an open - drain output structure or can be 3 - stated, a pull - up resistor is required. if the device generating the interrupt has a totem pole outpu t structure and cannot be 3 - stated, a pull - up resistor is not required. the interrupt inputs should not be left floating. i2c bus master
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 7 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic device addressing following a start condition the bus master must output the address of the slave it isaccessing. the address of the PI4MSD5V9544A is shown in figure 4 . to conserve power, nointernal pull - up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. the last bit of the slave address de?nes the operation to be performed . when set to logic 1 a read is selected, while a logic 0 selects a write operation. figure 4 : device address control register following the successful acknowledgement of the slave address, the bus master will send a byte to the PI4MSD5V9544A , which w ill be stored in the control register. if multiple bytes are received by the PI4MSD5V9544A , it will save the last byte received. this register can be written and read via the i2c - bus. figure 5 : control register control register definition one or sever al scx/sdx downstream pair, or channel, is selected by the contents of the control register. this register is written after the PI4MSD5V9544A has been addressed. the 2 lsbs of the control byte are used to determine which channel is to be selected. when a c hannel is selected, the channel will become active after a stop condition has been placed on the i2c - bus. this ensures that all scx/sdx lines will be in a high state when t he channel is made active, so that no false conditions are generated at the time of connection. int 3 int 2 int1 int0 d3 b2 b1 b0 command x x x x x 0 x x no channel selected x x x x x 1 0 0 channel 0 enabled x x x x x 1 0 1 channel 1 enabled x x x x x 1 1 0 channel 2 enabled x x x 0 x 1 1 1 channel 3 enabled 0 0 0 0 0 0 0 0 no channe l selected; power - up default state control register: write channel selection; read channel status.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 8 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic interrupt handling the PI4MSD5V9544A provides 4 interrupt inputs, one for each channel and one open - drain interrupt output. when an interrupt is generated by any device, it will be detected by the PI4MSD5V9544A and the interrupt output will be driven low. the channel need not be active for detection of the interrupt. a bit is also set in the control byte. bits 7:4 of the control byte correspond to channel 3 to channel 0 of the PI4MSD5V9544A , respectively. therefore, if an interrupt is generated by any device connected to channel 2, the state of the interrupt inputs is loaded into the control register when a read is accomplished. likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. the master can then address the PI4MSD5V9544A and read the contents of the control byte to determine which channel contains the device generating the interrupt. the master can then recon?gure the PI4MSD5V9544A to select this channel, and locate the device generating the interrupt and clear it. the interrupt clears when the deviceoriginating the interrupt clears. it should be noted that more than one device can pro vide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt.the interrupt inputs may be used as general - purpose inputs if the interrupt function is not required. if unused, interrupt i nput s must be connected to vcc through a pull - up resistor. int3 int2 int1 int0 d3 d 2 b1 b0 command 0 0 x 0 x x x x no interrupt on channel 0 1 interrupt on channel 0 0 0 0 x x x x x no interrupt on channel 1 1 interrupt on channel 1 x 0 x x x x x x no interrupt on channel 2 1 interrupt on channel 2 0 x x x x x x x no interrupt on channel 3 1 interrupt on channel 3 control register read interrupt remark: several interrupts can be active at the same time. for example: i nt3 = 0,int2 = 1, int1 = 1, int0 = 0, means that there is no interrupt on channel 0 andchannel 3, and there is an interrupt on channel 1 and on channel 2. power - on reset when power is applied to vcc , an internal power - on reset (por) holds the pi4msd5v954 4a in a reset condition until vcc has reached vpor. at this point, the reset condition is released and the PI4MSD5V9544A registers and i2c - bus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. th ereafter, vcc must be lowered below 0.2 v for at least 5 u s in order to reset the device.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 9 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic voltage translation the pass gate transistors of the PI4MSD5V9544A are constructe d such that the vcc voltage can be used to limit the maximum voltage that is passe d from one i2c - bus to another. figure 6 : vpass voltage vs vcc figure 6 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in section dc electrical characteristics of this data sheet). in order for the PI4MSD5V9544A to act as a voltage translator, the v pass voltage should be equal to, or lower than the lowest bus voltage. fo r example, if the main bus was running at 5 v, and the downstream buses were 3.3 v and 2.7 v, then v pass should be equal to or below 2.7 v to clamp the downstream bus voltages effectively. looking at figure 6 , we see that v pass (max) is at 2.7 v when the PI4MSD5V9544A supply voltage is 3.5 v or lower so the PI4MSD5V9544A supply voltage could be set to 3.3 v . pull - up resistors can then be used to bring the bus voltages to their appropriate levels i2c bus the i2c - bus is for 2 - way, 2 - line communication between dif ferent ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull - up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time are interpreted as control signals figure 7 : bit transfer
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 10 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic both data and clock lines remain high when the bus is not busy. a high - to - low tra nsition of the data line while the clock is high is defined as the start condition (s). a low - to - high transition of the data line while the clock is high is defined as the stop condition (p) figure 8 . definition of start and stop conditions a device ge nerating a message is a transmitter, a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves figure 9 . system configuration the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of 8 bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also, a master must generate an acknowledge after the reception of each byte t hat has been clocked out of the slav e transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse so that the sda line is stable low during the high period of the acknowledge relat ed clock pulse; set - up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enabl e the master to generate a stop condition. figure 10 . acknowledgment on i2c bus
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 11 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic data is transmitted to the PI4MSD5V9544A control regist er using the write mode shown in bellow figure 11 . write control register data is transmitted to the PI4MSD5V9544A control register us ing the write mode shown in bellow figure 1 2 . read control register
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 0 1 5 - 0 7 - 0 0 3 5 pt0 5 25 - 4 8 / 1 8 /1 5 12 pi4 msd5v954 4a 4 channel i2c /smb us multiplexer w ith i nterrupt logic mechanical information tssop - 20 ( l ) ordering information part no. package code package PI4MSD5V9544Al e x l 20 - pin,173 mil wide tssop , tape &reel note: ? e = pb - free and green ? addi ng x suffix = tape /r eel pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to i mprove design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circu itry embodied in pericom product. the company makes no representations that circuitry de scribed herein is free from patent infringement or other rights, of pericom .

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